The increasing ESD challenges for IP vendors and Suppliers

 With ESD and Latch-up becoming greater challenges at advanced technology nodes, it is becoming imperative for IP vendors and customers to be aware of the ESD risks associated with integrating an IP block or multiple IP blocks into a final product.  A brief discussion will present various design approaches IP providers can take and IP customers need to be aware of, to help ensure that an IP block does not experience ESD failures in the final product.

Serge Maginot, CEO of Tiempo, will present how Tiempo clockless IPs can be integrated into standard circuits to deliver unprecedented performance with ultra-low power.  Tiempo asynchronous IPs (MCUs and crypto-processors) are described in standard SystemVerilog and allow to reduce power consumption by a factor five for embedded electronic applications.

Turn your engineering cost center into an IP profit center

Many companies have untapped internal semiconductor IP assets that can be better leveraged for future internal projects and generate new additional revenue streams for their department.  Major semiconductor companies have learned how to do this and this presentation will explain how this is done and how your company can do it too.

Leveraging Your On-chip Networks and Maximizing Multi-layer Bus Designs

With the rapid development of SoCs being critical to maintaining a competitive edge in the market, designers face an ongoing challenge: How to design increasingly complex SoCs more affordably, rapidly and efficiently?  With cores and frequencies constantly scaling, traditional multi-layer AHB frameworks no longer deliver sufficient results. Sonics has been at the forefront of solving these design challenges for more than a decade—offering designers silicon-proven, on-chip communications solutions that enable rapid deployment of advanced SoCs, regardless of core protocol, frequency, or power considerations. With Sonics’ latest generation of product, SNAP, designers can cost-effectively simplify their on-chip networks for complex, embedded SoCs.

The Need for a New Breed of Embedded NVM

New and changing markets and applications are proliferating the use of non-volatile memory IP in a wide range of SoCs.  The increasing need for more cost-effective and secure data and code storage, analog trimming and calibration, and encryption key storage, along with field programmability, has created an opportunity for antifuse-based embedded OTP to replace more traditionally types of NVM – including ROM, Flash and eFuse – in many instances.  This brief presentation will discuss the driving factors towards the use of OTP IP and the attributes required by this emerging type of NVM.

Can You Trust Your IP Vendor? How Not to Lose Sleep Over it

Horror stories about IP-related project failures pervade the web, but what really matters is whether or not you can trust the people providing your IP. Over 16 years we've learned how to be a trustworthy IP vendor by listening carefully, responding quickly, upholding our commitments, and working more peer-to-peer than salesperson-to-customer. Here we'll describe what we've learned, and share some tips to help you evaluate the trustworthiness of any vendors you might consider.

Ultra Low Power CoolFlux DSP Cores Sweetening Your Green Chip Dreams

 With power consumption becoming a greater worry with every new technology node, silicon IP adopters need to place low power consumption of licensed cores high on their checklist. This presentation will explain how NXP’s licensable CoolFlux DSP cores contribute to cool down their chip designs while also avoiding high cost of ownership nightmares IP licensing often brings.

Rest in the comfort and security of knowing you have Selected the Optimum Memory IPs

To select optimum memory IPs, designers evaluate critical factors. These are architectural, structural, and cost factors. Designer need to make these decisions quickly, using automation and quickly achieve success for their target applications. Achieving well characterized, portable, robust, and cost effective memory IPs will be presented. These will include SRAM-1T, SRAM-6T, ROM, Register File, and CAM blocks. Optimum Memory IPs can help to differentiate SOC designs for ultra low-power, ultra low-leakage and high performance applications. Designers can select good memory IPs and have a pleasant sleep.

Ethernet is scaling from 1Gbps to 10/100Gbps in market segments such as Data center, Switching, and Storage devices. With Virtualization and Cloud Computing,  Network Security at lower layers of the network stack is quintessential. The security subsystem solution for addressing such complex problems have to be beyond crypto engines and with deep knowledge in networking and very high data rate applications. Posedge offers differentiated, high value, complete IP solutions to address these markets and the challenges they present.